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authorIwan Kawrakow <iwan.kawrakow@gmail.com>2024-06-10 11:40:32 +0300
committerIwan Kawrakow <iwan.kawrakow@gmail.com>2024-06-22 12:02:50 +0300
commit9e3dc8c4326ae5281c5abb9a4af349e47289cb30 (patch)
tree3ce8f8005cf8a159df2c8e07c4422c058af5def9 /sgemm.cpp
parentae1e77c5dee9b513e0b710075ef6713ede821b3c (diff)
iqk_mul_mat: slightly better fp16 with 16 vector registers
2x6 (Nx x Ny) tiles instead of 3x4. We get 142.7 t/s on the Ryzen-5975WX up from 138 t/s. We use Nx registers to preload the fp16 weights, so total registers required is Nx * (Ny + 1), so 15 in the case of of 3 x 4 tiles and 14 for 2 x 6 tiles. I guess, the one spare register helps. But maybe it is just a matter of how things get loaded into the cache. On the 7950X I did try 3 x 8 and it did not perform as well as 5 x 5.
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