From 154e0d75fccf1784fe9ff6fd76a630b66563da3d Mon Sep 17 00:00:00 2001 From: Kawrakow <48489457+ikawrakow@users.noreply.github.com> Date: Sat, 27 Jul 2024 07:55:01 +0200 Subject: Merge mainline llama.cpp (#3) * Merging mainline - WIP * Merging mainline - WIP AVX2 and CUDA appear to work. CUDA performance seems slightly (~1-2%) lower as it is so often the case with llama.cpp/ggml after some "improvements" have been made. * Merging mainline - fix Metal * Remove check --------- Co-authored-by: Iwan Kawrakow --- ggml-sycl/mmvq.hpp | 27 --------------------------- 1 file changed, 27 deletions(-) delete mode 100644 ggml-sycl/mmvq.hpp (limited to 'ggml-sycl/mmvq.hpp') diff --git a/ggml-sycl/mmvq.hpp b/ggml-sycl/mmvq.hpp deleted file mode 100644 index 049b43d4..00000000 --- a/ggml-sycl/mmvq.hpp +++ /dev/null @@ -1,27 +0,0 @@ -// -// MIT license -// Copyright (C) 2024 Intel Corporation -// SPDX-License-Identifier: MIT -// - -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// - -#ifndef GGML_SYCL_MMVQ_HPP -#define GGML_SYCL_MMVQ_HPP - -#include "common.hpp" - - -void ggml_sycl_op_mul_mat_vec_q( - ggml_backend_sycl_context & ctx, - const ggml_tensor *src0, const ggml_tensor *src1, ggml_tensor *dst, - const char *src0_dd_i, const float *src1_ddf_i, const char *src1_ddq_i, - float *dst_dd_i, const int64_t row_low, const int64_t row_high, - const int64_t src1_ncols, const int64_t src1_padded_row_size, - const dpct::queue_ptr &stream); - -#endif // GGML_SYCL_MMVQ_HPP -- cgit v1.2.3